Chiplets and Advanced Packaging Explained Without the Marketing

For most of the industry's history a processor was one piece of silicon, and making it better meant making that piece bigger or denser. Both routes have become difficult, and the response has been to stop building monolithic chips and start assembling them from smaller pieces. The reasoning behind this shift is largely economic, and understanding the economics makes the engineering choices considerably clearer.

Yield is the whole argument

Manufacturing defects occur at a roughly constant rate per unit area. A large die therefore has a much higher probability of containing at least one fatal defect than a small one, and the relationship is not linear — doubling the area more than doubles the loss. Beyond a certain size the proportion of working dies falls low enough that the economics stop working entirely. Splitting the same total silicon into four smaller pieces means a defect ruins a quarter of the design rather than all of it, and the yield improvement can be dramatic. Technical breakdowns of this arithmetic, including the manufacturing analysis at the manufacturing coverage on this site, tend to present it as the primary motivation with everything else following from it.

Mixing processes is the second advantage

Not every part of a processor benefits equally from the newest manufacturing process. Logic scales well. Analogue circuits, input-output interfaces and memory scale poorly, and building them on an expensive leading-edge process wastes capacity that has no alternative use. Disaggregation lets each function sit on the process that suits it: compute cores on the newest node, interfaces and controllers on a mature, cheaper one. The saving is substantial and it also relieves pressure on the leading-edge capacity that is perpetually oversubscribed.

• Compute dies on the most advanced available process
• Input-output and analogue functions on mature nodes
• Memory stacked adjacent rather than integrated
• Optional accelerators added or omitted per product variant

Product flexibility, almost for free

Once a design is modular, product families become combinations rather than separate designs. Two compute dies for one segment, eight for another, the same interface die across the range. Each distinct monolithic design carries an enormous fixed cost in engineering and mask sets; reusing chiplets across a portfolio amortises that cost across far more units. This is why disaggregation appeared first in server products, where the range of required configurations is widest and the volumes justify the packaging complexity.

What it costs

Connections that were previously wires within a single die become links between separate pieces of silicon, and crossing that boundary costs energy and time. On-die communication is essentially free by comparison; die-to-die communication requires drivers, protocols and error handling. Advanced packaging exists to make that crossing as cheap as possible — placing dies on a silicon interposer with very fine wiring, or bonding them directly face to face — but the penalty never reaches zero. A design partitioned along a boundary that carries heavy traffic will perform worse than the monolithic equivalent, which makes partitioning a first-order architectural decision rather than a packaging detail.

Thermal and test complications

Stacking components vertically improves bandwidth and creates a heat removal problem, since the layer in the middle has no direct path to a cooling surface. This constrains what can be placed where, and it is one reason memory rather than logic usually goes on top. Testing changes too: a package assembled from several dies is only as good as its worst component, so each piece must be verified as known-good before assembly, and the industry has invested heavily in test methodology precisely because a defective chiplet discovered after bonding wastes everything around it.

Standards and the open question

Most current designs use chiplets from a single company, connected by that company's own interfaces. The more interesting possibility is a market where dies from different vendors interoperate, which requires agreed electrical and protocol standards. Work in this direction is well advanced and adoption is gradual, because interoperability requires not only signalling agreement but shared conventions for test, thermal behaviour, packaging tolerances and liability when an assembled part fails. Those commercial questions are harder than the technical ones.

Design tools had to change too

Partitioning a processor across several dies is not only a manufacturing decision; it alters the entire design flow. Timing must be closed across a boundary whose electrical characteristics differ from on-die wiring. Power delivery has to be planned for an assembly rather than for a single piece of silicon. Thermal simulation becomes a three-dimensional problem with components heating each other. Verification must cover the assembled system, including the failure modes introduced by the links themselves. Much of the tooling to do this well arrived after the first products shipped, which is why early disaggregated designs were built by companies with the resources to solve those problems internally, and why the approach has spread only as commercial tools caught up.

What to watch

When assessing a new product built this way, the interesting figures are not the chiplet count. Look at the bandwidth and energy cost of the die-to-die links, since those determine whether the partitioning was well chosen. Look at how memory is attached, because that increasingly limits real workloads. And look at whether the same components appear across multiple products, which indicates a genuine modular strategy rather than a monolithic design that happened to be cut into pieces.